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Effect of Underlap On Device Performance of GaN Based DG-MOSFET
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GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.
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